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author | Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> | 2024-02-23 10:28:08 +0900 |
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committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-02-29 03:11:56 +0000 |
commit | 9620b3d152e0c939d06b900aa65dba3f26ebe2e2 (patch) | |
tree | 65915cf8cc90ada5c4c3ec60419600824ded1cc7 /src/mainboard/intel/kblrvp/spd/Makefile.mk | |
parent | 10291e800ca45c722ac43d205c0b8ed46633ab56 (diff) |
include/device/azalia_device.h: Correct location2 shift to 28 bits
The location is specified to be in range of 29:24, which is further
divided into upper bits (location2) [5:4] and lower bits (location1)
[3:0].
This also corrects the resulting values of clevo/l140mu.
References:
- Intel High Definition Audio Specification, rev. 1.0a, page 178,
Figure 74. Configuration Data Structure.
TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the
same binary.
Change-Id: Ia5a3431b70783cb88e866d0fd8ea5530100f3d52
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80727
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp/spd/Makefile.mk')
0 files changed, 0 insertions, 0 deletions