mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3

Add support for Kaby Lake RVP3.
Use kunimitsu at commit 028200f as base.

Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel
LPDDR3 DIMM.

* Update board name to kblrvp
* Remove fsp 1.1 specific code( As Kabylake uses fsp2.0)
* Remove board id function.
* Remove unused spd & add rvp3 spd file.

This is an initial commit does not have full support to boot.
Will add more CLs to boot Chrome OS with depthcharge.

Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 46 insertions, 0 deletions

diff --git a/src/mainboard/intel/kblrvp/ec.c b/src/mainboard/intel/kblrvp/ec.c
new file mode 100644
index 0000000000..235ecab9ef
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/ec.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+	printk(BIOS_DEBUG, "mainboard: EC init\n");
+
+	if (acpi_is_wakeup_s3()) {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S3_WAKE_EVENTS);
+
+		/* Disable SMI and wake events */
+		google_chromeec_set_smi_mask(0);
+
+		/* Clear pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+
+		/* Restore SCI event mask */
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+	} else {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S5_WAKE_EVENTS);
+	}
+
+	/* Clear wake event mask */
+	google_chromeec_set_wake_mask(0);
+}