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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2020-04-29 14:27:03 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-05-11 08:37:14 +0000
commitf0967a7e043ba503c6e1c0402213fc342939ddb8 (patch)
tree4e000c10b78533e88a9004f06940b1dc0a1b2feb /src/mainboard/intel/jasperlake_rvp
parent6d500a24762a936ee2a8478fb8110df1bfed1cce (diff)
mb/intel/jasperlake_rvp: Add support for SMI handler
SMI handler was not present in jasperlake rvp to handle wake events when platform goes to sleep or shutdown or s0ix. Adding this support for board which supports chromeec. BUG=None BRANCH=None TEST=Check wake event on board and platform wakes up due to events lid wake event or power button press. Change-Id: I8e35955b06d6efaf9275ec03f519c9bcaa9ba345 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/mainboard/intel/jasperlake_rvp')
-rw-r--r--src/mainboard/intel/jasperlake_rvp/Makefile.inc2
-rw-r--r--src/mainboard/intel/jasperlake_rvp/smihandler.c38
2 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/Makefile.inc
index 28684e2fa7..a8c261b5c8 100644
--- a/src/mainboard/intel/jasperlake_rvp/Makefile.inc
+++ b/src/mainboard/intel/jasperlake_rvp/Makefile.inc
@@ -19,6 +19,8 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
ramstage-y += board_id.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
subdirs-y += ../common
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
diff --git a/src/mainboard/intel/jasperlake_rvp/smihandler.c b/src/mainboard/intel/jasperlake_rvp/smihandler.c
new file mode 100644
index 0000000000..c06da29ae2
--- /dev/null
+++ b/src/mainboard/intel/jasperlake_rvp/smihandler.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <baseboard/variants.h>
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/smm.h>
+#include <elog.h>
+#include <intelblocks/smihandler.h>
+#include <baseboard/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+
+ return 0;
+}
+
+void elog_gsmi_cb_mainboard_log_wake_source(void)
+{
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+}