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authorJulien Viard de Galbert <jviarddegalbert@online.net>2017-11-06 13:16:30 +0100
committerPatrick Georgi <pgeorgi@google.com>2017-11-07 12:33:18 +0000
commit66c210ae3790feb11e89e2d6353f1ce26966d5b9 (patch)
tree5f52f455c3d7fc94b67bd03bcef18fba51845f1a /src/mainboard/intel/harcuvar/Makefile.inc
parentf528195bdf141e84d3121411d2cbe32f5938dd72 (diff)
mainboard/intel/harcuvar: update to set the HSIO lines configuration
Change-Id: Ifc3423ff983fb631edcab087d04742937b25ef86 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/22310 Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/harcuvar/Makefile.inc')
-rw-r--r--src/mainboard/intel/harcuvar/Makefile.inc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/harcuvar/Makefile.inc b/src/mainboard/intel/harcuvar/Makefile.inc
index ba88569c8a..d100688fe0 100644
--- a/src/mainboard/intel/harcuvar/Makefile.inc
+++ b/src/mainboard/intel/harcuvar/Makefile.inc
@@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2014 - 2017 Intel Corporation.
+## Copyright (C) 2017 Online SAS.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@@ -16,9 +17,11 @@
subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd
romstage-y += boardid.c
+romstage-y += hsio.c
ramstage-y += ramstage.c
ramstage-y += boardid.c
+ramstage-y += hsio.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c