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| author | Gabe Black <gabeblack@google.com> | 2012-03-30 14:33:02 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-01 20:01:18 +0200 |
| commit | 599e204efc5a55eb388a2ff11afb0e2196c21875 (patch) | |
| tree | 1ecb4dd00dcd6c44e5eb9f1ad4d6cb3b3aee042c /src/mainboard/intel/emeraldlake2/romstage.c | |
| parent | 8172d0be978d74eaaf103b592b505385db105f67 (diff) | |
Clean up Emerald Lake 2 mainboard directory
Change-Id: I4a64a56dda22050a31232807096e15565a665377
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/967
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/emeraldlake2/romstage.c')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 0cf113b9f3..879756bf71 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -242,7 +242,7 @@ void main(unsigned long bist) /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - setup_pch_gpios(&link_gpio_map); + setup_pch_gpios(&emeraldlake2_gpio_map); setup_sio_gpios(); /* Early SuperIO setup */ |