Add support for Intel Emerald Lake 2 CRB

This adds support for Intel's Emerald Lake 2 board.

Change-Id: Ifaeeac9d52fe655324ee29df5f7187b89b35f73a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/951
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

9 files changed, 726 insertions, 0 deletions

diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
new file mode 100644
index 0000000000..65202cb6d4
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (CRHW)
+{
+	Name(_HID, EISAID("GGL0001"))
+
+	Method(_STA, 0, Serialized)
+	{
+		Return (0xb)
+	}
+
+	Method(CHSW, 0, Serialized)
+	{
+		Name (WSHC, Package() { VBT3 })
+		Return (WSHC)
+	}
+
+	Method(FWID, 0, Serialized)
+	{
+		Name (DIW1, "")
+		ToString(VBT5, 63, DIW1)
+		Name (DIWF, Package() { DIW1 })
+		Return(DIWF)
+	}
+
+	Method(FRID, 0, Serialized)
+	{
+		Name (DIR1, "")
+		ToString(VBT6, 63, DIR1)
+		Name (DIRF, Package() { DIR1 })
+		Return (DIRF)
+	}
+
+	Method(HWID, 0, Serialized)
+	{
+		Name (DIW0, "")
+		ToString(VBT4, 255, DIW0)
+		Name (DIWH, Package() { DIW0 })
+		Return (DIWH)
+	}
+
+	Method(BINF, 0, Serialized)
+	{
+		Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+		Return (FNIB)
+	}
+
+	Method(GPIO, 0, Serialized)
+	{
+		Name(OIPG, Package() {
+			Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
+			Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
+			Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect
+			Package() { 0x100, 0,  9, "CougarPoint" }, // debug header gpio
+			Package() { 0x101, 0, 10, "CougarPoint" }, // debug header gpio 1
+			Package() { 0x102, 0, 12, "CougarPoint" }, // debug header gpio 2
+			Package() { 0x103, 0, 13, "CougarPoint" }, // debug header gpio 3
+			Package() { 0x104, 0, 14, "CougarPoint" }, // debug header gpio 4
+			Package() { 0x105, 0, 15, "CougarPoint" }, // debug header gpio 5
+			Package() { 0x106, 0, 24, "CougarPoint" }, // debug header gpio 6
+			Package() { 0x107, 0, 26, "CougarPoint" }, // debug header gpio 7
+		})
+		Return (OIPG)
+
+	}
+
+	Method(VBNV, 0, Serialized)
+	{
+		Name(VNBV, Package() {
+			// See src/vendorcode/google/chromeos/Kconfig
+			// for the definition of these:
+			CONFIG_VBNV_OFFSET,
+			CONFIG_VBNV_SIZE
+		})
+		Return(VNBV)
+	}
+
+	Method(VDAT, 0, Serialized)
+	{
+		Name(TAD0,"")
+		ToBuffer(CHVD, TAD0)
+		Name (TADV, Package() { TAD0 })
+		Return (TADV)
+	}
+
+	Method(FMAP, 0, Serialized)
+	{
+		Name(PAMF, Package() { VBT9 })
+		Return(PAMF)
+	}
+
+	Method(MECK, 0, Serialized)
+	{
+		Name(HASH, Package() { MEHH })
+		Return(HASH)
+	}
+
+	Method(MLST, 0, Serialized)
+	{
+		Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+			   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+		})
+		Return (TSLM)
+	}
+}
diff --git a/src/mainboard/intel/emeraldlake2/acpi/ec.asl b/src/mainboard/intel/emeraldlake2/acpi/ec.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/ec.asl
diff --git a/src/mainboard/intel/emeraldlake2/acpi/ivybridge_pci_irqs.asl b/src/mainboard/intel/emeraldlake2/acpi/ivybridge_pci_irqs.asl
new file mode 100644
index 0000000000..6f2d3e9166
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/ivybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for IvyBridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 20 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 20 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 21 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 16 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl b/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl
new file mode 100644
index 0000000000..6b15331b81
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/mainboard.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (PWRB)
+{
+	Name(_HID, EisaId("PNP0C0C"))
+
+	// Wake
+	Name(_PRW, Package(){0x1d, 0x05})
+}
diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl
new file mode 100644
index 0000000000..fea92d05bd
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// NVS has a flag to determine USB policy in S3
+	if (S3U0) {
+		Store (One, GP47)   // Enable USB0
+	} Else {
+		Store (Zero, GP47)  // Disable USB0
+	}
+
+	// NVS has a flag to determine USB policy in S3
+	if (S3U1) {
+		Store (One, GP56)   // Enable USB1
+	} Else {
+		Store (Zero, GP56)  // Disable USB1
+	}
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl b/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000000..f9031846c2
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 20 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 20 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 21 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 16 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl
new file mode 100644
index 0000000000..f803aaf8b9
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#undef SIO_ENABLE_FDC0           // pnp 2e.0: Disable Floppy Controller
+#undef SIO_ENABLE_INFR           // pnp 2e.a: Disable Consumer IR
+
+#define SIO_ENABLE_PS2K          // pnp 2e.5: Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M          // pnp 2e.6: Enable PS/2 Mouse
+#define SIO_ENABLE_COM1          // pnp 2e.1: Enable Serial Port 1
+#define SIO_ENABLE_ENVC          // pnp 2e.4: Enable Environmental Controller
+#define SIO_ENVC_IO0      0x700  // pnp 2e.4: io 0x60
+#define SIO_ENVC_IO1      0x710  // pnp 2e.4: io 0x62
+#define SIO_ENABLE_GPIO	  	 // pnp 2e.7: Enable GPIO
+#define SIO_GPIO_IO0      0x720  // pnp 2e.7: io 0x60
+#define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
+
+#include "../../../../superio/smsc/sio1007/acpi/superio.asl"
diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
new file mode 100644
index 0000000000..d96d955bbc
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get CPU Temperature from PECI via SuperIO TMPIN3
+			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Return (CTOK (\F2ON))
+			}
+
+			// PECI raw value is an offset from Tj_max
+			Subtract (255, Local0, Local1)
+
+			// Handle values greater than Tj_max
+			If (LGreaterEqual (Local1, \TMAX)) {
+				Return (CTOK (\TMAX))
+			}
+
+			// Subtract from Tj_max to get temperature
+			Subtract (\TMAX, Local1, Local0)
+			Return (CTOK (Local0))
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (\F0OF))
+			} Else {
+				Return (CTOK (\F0ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (\F1OF))
+			} Else {
+				Return (CTOK (\F1ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (\F2OF))
+			} Else {
+				Return (CTOK (\F2ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (\F3OF))
+			} Else {
+				Return (CTOK (\F3ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (\F4OF))
+			} Else {
+				Return (CTOK (\F4ON))
+			}
+		}
+
+		Name (_AL0, Package () { FAN0 })
+		Name (_AL1, Package () { FAN1 })
+		Name (_AL2, Package () { FAN2 })
+		Name (_AL3, Package () { FAN3 })
+		Name (_AL4, Package () { FAN4 })
+
+		PowerResource (FNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (0, \FLVL)
+				Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (1, \FLVL)
+				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (1, \FLVL)
+				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (2, \FLVL)
+				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP2, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 2)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (2, \FLVL)
+				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (3, \FLVL)
+				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP3, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 3)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (3, \FLVL)
+				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP4, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 4)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		Device (FAN0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { FNP0 })
+		}
+
+		Device (FAN1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { FNP1 })
+		}
+
+		Device (FAN2)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 2)
+			Name (_PR0, Package () { FNP2 })
+		}
+
+		Device (FAN3)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 3)
+			Name (_PR0, Package () { FNP3 })
+		}
+
+		Device (FAN4)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 4)
+			Name (_PR0, Package () { FNP4 })
+		}
+	}
+}
+
diff --git a/src/mainboard/intel/emeraldlake2/acpi/video.asl b/src/mainboard/intel/emeraldlake2/acpi/video.asl
new file mode 100644
index 0000000000..3ececa912b
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/acpi/video.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
+