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authorMichael Niewöhner <foss@mniewoehner.de>2020-12-21 17:09:08 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2021-01-21 18:14:09 +0000
commitf9544da6c42ccaf43d926191d6c4e0f914d79a59 (patch)
treeb1ea480649dbcda908210b983cb4d42d800c4826 /src/mainboard/intel/elkhartlake_crb
parentfccc24f063acb2470ba919237b0056c6afecd4d9 (diff)
mb/intel/leafhill: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms by adding an appropriate early gpio table in the bootblock. The soc code gets dropped in CB:49410. Change-Id: Ie1e53e72c65fdcfe4be2e01134873aa7858c28ff Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49416 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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