diff options
| author | Keith Hui <buurin@gmail.com> | 2024-02-05 16:11:26 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-07 22:39:18 +0000 |
| commit | c36b5ea18983e3dbb021ae3012698d1357dcdf66 (patch) | |
| tree | f2575cdcf079c721cf89bba887cf2d28b791a256 /src/mainboard/intel/dq67sw/devicetree.cb | |
| parent | 51a01bdcd65370c29342f51a29fa5741447f09dc (diff) | |
mb/*: Copy bd82x6x boards' USB port config into devicetree
For mainboards using southbridge/intel/bd82x6x, copy the contents
of mainboard_usb_ports array into southbridge devicetree. In-line
comments are maintained.
Boards also capable of using MRC raminit are done in a separate
patch.
Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dq67sw/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/dq67sw/devicetree.cb | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb index f29b772e8a..6a28bcc1bf 100644 --- a/src/mainboard/intel/dq67sw/devicetree.cb +++ b/src/mainboard/intel/dq67sw/devicetree.cb @@ -14,6 +14,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref mei1 on end # Management Engine Interface 1 device ref me_ide_r on end # Management Engine IDE-R device ref me_kt on end # Management Engine KT |