From c36b5ea18983e3dbb021ae3012698d1357dcdf66 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 5 Feb 2024 16:11:26 -0500 Subject: mb/*: Copy bd82x6x boards' USB port config into devicetree For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/intel/dq67sw/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/mainboard/intel/dq67sw/devicetree.cb') diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb index f29b772e8a..6a28bcc1bf 100644 --- a/src/mainboard/intel/dq67sw/devicetree.cb +++ b/src/mainboard/intel/dq67sw/devicetree.cb @@ -14,6 +14,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref mei1 on end # Management Engine Interface 1 device ref me_ide_r on end # Management Engine IDE-R device ref me_kt on end # Management Engine KT -- cgit v1.2.3