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authorAngel Pons <th3fanbus@gmail.com>2020-11-14 16:34:35 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-11-22 19:18:57 +0000
commit59996e03774e5430bd94a8a0eb51a927a1ef4eb1 (patch)
tree306b981a5220095e5c0bacaea92e65192afed894 /src/mainboard/intel/dg43gt/hda_verb.c
parentd029a579badd2e71e87b84f66e5fbe87c1651bee (diff)
nb/intel/sandybridge: Use one sequence for write leveling
In order to run a write leveling test, one needs to unset the Qoff bit in MR1, then run the test, and finally set Qoff again. The current IOSAV sequence uses two subsequences to perform the test, while the other two are unused. It is possible to perform the two necessary MR1 updates in the same sequence, which can potentially improve runtime (not measured). Since `write_mrreg` is no longer used, it is necessary to handle address mirroring explicitly. This can be accomplished with the recently-added `ddr3_mirror_mrreg` function, which is also used in `write_mrreg`. Tested on Asus P8H61-M PRO, still boots. Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dg43gt/hda_verb.c')
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