diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 01:02:28 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 17:04:46 +0000 |
| commit | b21bffae0ce5dee5d316ad544ccc6dedbc4475a1 (patch) | |
| tree | 5affe6f49cf0c7b7cb5b95d6cd5dd928d624dd8b /src/mainboard/intel/dcp847ske | |
| parent | 65e5b100e2133a305ba1f471a23d75dc37a2224d (diff) | |
sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE
Make it default to 0x400, which is what the touched southbridges use.
Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel/dcp847ske')
| -rw-r--r-- | src/mainboard/intel/dcp847ske/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index e81b4b66b4..c9f3dcd42f 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -18,7 +18,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, + .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = CONFIG_HPET_ADDRESS, |