SNB+MRC boards: Migrate MRC settings to devicetree

For Sandy Bridge boards with MRC raminit support, migrate as much
MRC settings to devicetree as possible, to stop mainboard code from
needlessly overwriting entire PEI data structure, so they will not
interfere with upcoming transition to one standard Haswell way of
providing SPD info to northbridge.

Some exceptions allowed are described below and in code comments.

SPD-related items are kept out of devicetree for now. They will be
migrated (with a different representation) with the Haswell SPD
transition.

google/{butterfly,link,parrot,stout} have max DDR3 frequency set in
pei_data to 1600 (2*800), but in devicetree to 666. The reason for the
difference seems to be problems with native raminit code. These are
converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an
added "fix me" tag. asus/p8x7x-series also needs the same treatment,
based on testing various memory on p8z77-m hardware.

TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested.

Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

2 files changed, 24 insertions, 35 deletions

diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index 885043649c..37304f2167 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -11,6 +11,25 @@ chip northbridge/intel/sandybridge
 	# Enable DVI Hotplug with 6ms pulse
 	register "gpu_dp_b_hotplug" = "0x06"
 
+	# 1333MHz RAM frequency
+	register "max_mem_clock_mhz" = "666"
+
+	register "usb_port_config" = "{
+		{1, 0, 0x0040},
+		{1, 0, 0x0040},
+		{1, 1, 0x0040},
+		{1, 1, 0x0040},
+		{1, 2, 0x0040},
+		{1, 2, 0x0040},
+		{1, 3, 0x0040},
+		{0, 3, 0x0040},
+		{0, 4, 0x0040},
+		{0, 4, 0x0040},
+		{0, 5, 0x0040},
+		{0, 5, 0x0040},
+		{0, 6, 0x0040},
+		{0, 6, 0x0040},	}"
+
 	device domain 0 on
 		device ref host_bridge on  end	# Host bridge
 		device ref peg10 off end	# PCIe Bridge for discrete graphics
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index e7b936ae35..d0decb4602 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -1,44 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <stdint.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#if CONFIG(USE_NATIVE_RAMINIT)
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#else
 #include <northbridge/intel/sandybridge/raminit.h>
-#endif
 #include <southbridge/intel/bd82x6x/pch.h>
 
-#if !CONFIG(USE_NATIVE_RAMINIT)
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	struct pei_data pei_data_template = {
-		.pei_version = PEI_VERSION,
-		.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
-		.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
-		.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
-		.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
-		.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
-		.wdbbar = 0x4000000,
-		.wdbsize = 0x1000,
-		.hpet_address = HPET_BASE_ADDRESS,
-		.rcba = (uintptr_t)DEFAULT_RCBA,
-		.pmbase = DEFAULT_PMBASE,
-		.gpiobase = DEFAULT_GPIOBASE,
-		.thermalbase = 0xfed08000,
-		.system_type = 0, // 0 Mobile, 1 Desktop/Server
-		.tseg_size = CONFIG_SMM_TSEG_SIZE,
-		.spd_addresses = { 0xa0, 0x00, 0xa2, 0x00 },
-		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
-		.ec_present = 0,
-		.gbe_enable = 1,
-		.max_ddr3_freq = 1333,
-		.usb_port_config = {
-#define USB_CONFIG(enabled, current, ocpin) { enabled, ocpin, 0x040 * current }
-#include "usb.h"
-		},
-	};
-	*pei_data = pei_data_template;
+	const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00};
+
+	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
+
+	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
-#endif