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authorKeith Hui <buurin@gmail.com>2024-02-05 16:44:38 -0500
committerMartin L Roth <gaumless@gmail.com>2024-06-08 00:08:33 +0000
commit51a57eb5ea782c3287719c8c7646ea726b14c78d (patch)
tree7ff3a6b1424750e66d4349f41eeb7fcc7b10ab77 /src/mainboard/intel/dcp847ske
parent1acb3e118bf0bdba8f13f62304425f8c21dad2c8 (diff)
mb/*: Add consolidated USB port config for SNB+MRC boards
For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using special values allocated for this consolidation. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/dcp847ske')
-rw-r--r--src/mainboard/intel/dcp847ske/devicetree.cb17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index f4e948f76c..8b10b6b36c 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -43,6 +43,23 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff
+ register "usb_port_config" = "{
+ {1, 1, 0}, /* back, towards HDMI plugs */
+ {1, 1, 0}, /* back, towards power plug */
+ {1, 1, 1}, /* half-width miniPCIe */
+ {1, 1, 1}, /* full-width miniPCIe */
+ {1, 1, 2}, /* front-panel header */
+ {1, 1, 2}, /* front-panel header */
+ {1, 1, 3}, /* front connector */
+ {0, 1, 3}, /* not available x7 */
+ {0, 1, 4},
+ {0, 1, 4},
+ {0, 1, 5},
+ {0, 1, 5},
+ {0, 1, 6},
+ {0, 1, 6}
+ }"
+
device ref xhci off end # USB xHCI
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2