From 51a57eb5ea782c3287719c8c7646ea726b14c78d Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 5 Feb 2024 16:44:38 -0500 Subject: mb/*: Add consolidated USB port config for SNB+MRC boards For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using special values allocated for this consolidation. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/intel/dcp847ske/devicetree.cb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/mainboard/intel/dcp847ske') diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index f4e948f76c..8b10b6b36c 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -43,6 +43,23 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + register "usb_port_config" = "{ + {1, 1, 0}, /* back, towards HDMI plugs */ + {1, 1, 0}, /* back, towards power plug */ + {1, 1, 1}, /* half-width miniPCIe */ + {1, 1, 1}, /* full-width miniPCIe */ + {1, 1, 2}, /* front-panel header */ + {1, 1, 2}, /* front-panel header */ + {1, 1, 3}, /* front connector */ + {0, 1, 3}, /* not available x7 */ + {0, 1, 4}, + {0, 1, 4}, + {0, 1, 5}, + {0, 1, 5}, + {0, 1, 6}, + {0, 1, 6} + }" + device ref xhci off end # USB xHCI device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 -- cgit v1.2.3