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| author | Matt Papageorge <matthewpapa07@gmail.com> | 2021-05-14 14:08:53 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-23 14:06:32 +0000 |
| commit | c8f926addac7f2bf8ea8836a31337430aa63db9f (patch) | |
| tree | ade01e39d164eaf9221cd4c4a406787adc5e32fe /src/mainboard/intel/dcp847ske/early_southbridge.c | |
| parent | 77fb9a0bb245acaa334cde2b4c72ff4dcf58f379 (diff) | |
mb/google/guybrush: Enable PCIe L1 Substates
This change enables L1.1 and L1.2 on all real Guybrush PCIe devices.
BUG=b:188123142
TEST=Boot to ChromeOS and verify L1SS are functional by dumping the
settings with "lspci -vv". Leave system on for 20 minutes and no hang.
Also perform 20 reboots and suspend operations
Cq-Depend: chrome-internal:4012927
Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/intel/dcp847ske/early_southbridge.c')
0 files changed, 0 insertions, 0 deletions