summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/d945gclf
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-22 15:24:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-28 17:24:48 +0200
commitcdfb46240b4bba8a112c85a5f5d26447e90378b3 (patch)
treed344b5c2916050e49975a3089ae81bb3c7a6c632 /src/mainboard/intel/d945gclf
parente5523b808b2a29a3049a21a3b0339e80fbeef42a (diff)
AGESA boards: Use devicetree for PCI bus enumeration
Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
0 files changed, 0 insertions, 0 deletions