diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-03 00:29:39 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 09:56:20 +0000 |
| commit | c85cce077cc9ded8f33b9b059ce0b165da618639 (patch) | |
| tree | 6911321c436c40374f2ca7a032524e528cec7a32 /src/mainboard/intel/d945gclf | |
| parent | 2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2 (diff) | |
mb/**/cmos.layout: Indent everything with tabs
Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
| -rw-r--r-- | src/mainboard/intel/d945gclf/cmos.layout | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index 58f96f03f1..41f967d7ab 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -4,69 +4,69 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums |