diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-29 14:46:19 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-07 17:23:16 +0000 |
| commit | bb5c255907378a5c5798b5dab3616df1e63d3ee7 (patch) | |
| tree | 6998607d8ef4942b7c547131c121cd25264f61d7 /src/mainboard/intel/d945gclf | |
| parent | 2ad8ffed6fc3d0865d8dc066dcbf6ef2e369794c (diff) | |
dptf: Add support for Running Average Power Limits
This change adds support for emitting the PPCC table, which describes
the ranges available as knobs for DPTF to tune. It can support min/max
power, min/max time window for averaging, and the minimum adjustment size
(granularity or step size) of each power limit. The current implementation
only supports PL1 and PL2.
BUG=b:143539650
TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
0 files changed, 0 insertions, 0 deletions