diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-01-07 16:53:43 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-19 16:32:57 +0100 |
| commit | a0ee532af76d5ecca3d87b080513d84695dc5321 (patch) | |
| tree | 306832cff20b286a74cdeb3fddde5231f0af02db /src/mainboard/intel/d945gclf | |
| parent | ec19fccf7614ae4405829ac0e71460ff18500ee8 (diff) | |
google/chell: Set FSP params for min assertion widths and serirq
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409
Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321212
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13009
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
0 files changed, 0 insertions, 0 deletions