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authorMario Scheithauer <mario.scheithauer@siemens.com>2022-11-24 08:38:19 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-11-25 15:44:46 +0000
commit68fb5437f9680428cbb7cf39c4a73911671a6359 (patch)
treea4ca0fe7503e7d241ed9f7550b76ffd7ddb92ffd /src/mainboard/intel/coffeelake_rvp
parent3627f2903c8597b8765117146cf2868daecfe305 (diff)
mb/siemens/mc_ehl2: Disable L1 prefetcher
As for mainboard mc_ehl1, a hard real-time dependency is also required for this mainboard. The L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: I07b27dd672533e693a6c2987d16f54333850760e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp')
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