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authorAngel Pons <th3fanbus@gmail.com>2020-11-19 21:50:33 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-23 16:01:53 +0000
commit075d123f6a57e4ef0f542f2f1f0b162b11cffe5a (patch)
treea3ca8cded1ec446486c86e43cff3740d20a0f05c /src/mainboard/intel/coffeelake_rvp
parent81ff33cffc103c184e002ccefe939efe2958a421 (diff)
nb/intel/sandybridge: Compute data timings independently
Use absolute values for the Rx and Tx bus timings instead of values relative to the CA (Command/Address) bus timing. This makes the calculations more accurate, less complex and less error-prone. Tested on Asus P8H61-M PRO, still boots. Training results do not seem to be affected by this patch, and the margins roughly have the same shape. Change-Id: I28ff1bdaadf1fcbca6a5e5ccdd456de683206410 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47771 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/coffeelake_rvp')
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