mb/intel/coffeelake_rvp: Add support for new board coffeelake RVP

Add support for new board coffeelake RVP.
This patch is a copy patch and copies entire coffeelake_rvp folder from
cannonlake_rvp.

Changes done on top of copy:
1. Change copyright year from 2017 to 2018
2. Rename Cannonlake to Coffelake whenever applicable
3. Update entries in Kconfig and Kconfig.name
4. Rename variant directories to match coffeelake boards

Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 233 insertions, 0 deletions

diff --git a/src/mainboard/intel/coffeelake_rvp/spd/Makefile.inc b/src/mainboard/intel/coffeelake_rvp/spd/Makefile.inc
new file mode 100644
index 0000000000..f7288566a4
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/spd/Makefile.inc
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2018 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = empty				# 0b000
+SPD_SOURCES += samsung_ddr4_4GB			# 0b001 Dual Channel 4GB
+SPD_SOURCES += samsung_lpddr4_8GB		# 0b001 Dual Channel 8GB
+SPD_SOURCES += empty				# 0b011
+SPD_SOURCES += empty				# 0b100
+SPD_SOURCES += empty				# 0b101
+SPD_SOURCES += empty				# 0b110
+SPD_SOURCES += empty				# 0b111
diff --git a/src/mainboard/intel/coffeelake_rvp/spd/empty.spd.hex b/src/mainboard/intel/coffeelake_rvp/spd/empty.spd.hex
new file mode 100644
index 0000000000..67b46cd239
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex b/src/mainboard/intel/coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex
new file mode 100644
index 0000000000..49db2374f4
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/spd/samsung_ddr4_4GB.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00
+00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08
+00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
+16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
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+0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31
+34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE
+00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00
+01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex
new file mode 100644
index 0000000000..d298629342
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/spd/samsung_lpddr4_8GB.spd.hex
@@ -0,0 +1,32 @@
+23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00
+48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd.h b/src/mainboard/intel/coffeelake_rvp/spd/spd.h
new file mode 100644
index 0000000000..036b5be888
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/spd/spd.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define RCOMP_TARGET_PARAMS	0x5
+
+void mainboard_fill_dq_map_ch0(void *dq_map_ptr);
+void mainboard_fill_dq_map_ch1(void *dq_map_ptr);
+void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);
+void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
new file mode 100644
index 0000000000..09bd303aff
--- /dev/null
+++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <stdint.h>
+#include <string.h>
+#include "spd.h"
+
+void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
+{
+	/* DQ byte map Ch0 */
+	const u8 dq_map[12] = {
+		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
+{
+	const u8 dq_map[12] = {
+		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
+{
+	/* DQS CPU<>DRAM map Ch0 */
+	const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
+
+	const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
+
+	if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))
+		memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
+	else
+		memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
+}
+
+void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
+{
+	/* DQS CPU<>DRAM map Ch1 */
+	const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
+
+	const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
+
+	if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU))
+		memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
+	else
+		memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+	/* Rcomp resistor */
+	const u16 RcompResistor[3] = { 100, 100, 100 };
+	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+	/* Rcomp target */
+	static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
+			80, 40, 40, 40, 30 };
+
+	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}