diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-12 16:55:54 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-16 15:23:37 +0000 |
| commit | 14cb828f4fd818c4d9d1bcf80db9e5a9fc2df19f (patch) | |
| tree | 913dc1f29c1cd979da8bca72306d77ffdb937a9b /src/mainboard/intel/cannonlake_rvp/romstage.c | |
| parent | 776b5ba017dfbe2df363381b7c58aad12518c805 (diff) | |
intel/cannonlake_rvp: Modify memory parameters to support LP4 board
Replace the support for Cannonlake U DDR4 board to Cannonlake U LPDDR4
platform.
TEST=Able to boot up on CNL U LPDDR RVP.
Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp/romstage.c')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/romstage.c | 16 |
1 files changed, 4 insertions, 12 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c index 03c5807c00..e0699da500 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage.c @@ -36,18 +36,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) { - mem_cfg->DqPinsInterleaved = 1; - mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */ - spd_index = 1; - } else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */ - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - spd_index = 2; - } - - printk(BIOS_DEBUG,"SPD INDEX =0x%u\n", spd_index); + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + spd_index = 2; struct region_device spd_rdev; |