diff options
author | zhaojohn <john.zhao@intel.com> | 2017-08-21 21:50:10 -0400 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-23 15:53:10 +0000 |
commit | 53461ad1f89f31a091d6e055dedbb9c0b014ac86 (patch) | |
tree | 73e24f986d505ea4f012f1a7b5ff06c817c17813 /src/mainboard/intel/cannonlake_rvp/chromeos.c | |
parent | 5bddcc48b82c1887c96077c85ba078cd427d1133 (diff) |
src/mainboard/intel/cannonlake: Add gpio support for cannonlake
Add gpio pins configuration for cannonlake rvp u/y boards.
Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc
Signed-off-by: john zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/cannonlake_rvp/chromeos.c')
-rw-r--r-- | src/mainboard/intel/cannonlake_rvp/chromeos.c | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c new file mode 100644 index 0000000000..b7dd91d4c0 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <rules.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} +#endif /* ENV_RAMSTAGE */ + +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} |