diff options
| author | Martin Roth <gaumless@gmail.com> | 2015-02-12 22:51:57 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2015-03-12 20:35:49 +0100 |
| commit | d08057aa20d8dff404ba9121a5d2052ae6575356 (patch) | |
| tree | 72c3bd33b2ad4645916b70a7fac9d3d730de256c /src/mainboard/intel/bayleybay_fsp | |
| parent | 48b3dbc7483f5404a2dfb3b8bb5f4bcf7d3c4b09 (diff) | |
intel/fsp_baytrail: Add PCI Root Port IRQ Routing
This change generates the ASL tables needed for the PCIe bridge routing.
It generates this ASL (swizzled for each of the 8 functions)
Name(RP1P, Package()
{
Package() {0x0000ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
Package() {0x0000ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
Package() {0x0000ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
Package() {0x0000ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
})
Name(RP1A, Package()
{
Package() {0x0000ffff, 0, 0, 20 },
Package() {0x0000ffff, 1, 0, 21 },
Package() {0x0000ffff, 2, 0, 22 },
Package() {0x0000ffff, 3, 0, 23 },
})
Device(RP01) {
Name(_ADR, 0x1c0001)
Name(_PRW, Package() {
0, 0
})
Method(_PRT,0) {
If(PICM) {
Return (RP1A)
} Else {
Return (RP1P)
}
}
}
Change-Id: Id51261c11f8457fe2150f2b646aafc4fe1ffec30
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8429
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/bayleybay_fsp')
| -rw-r--r-- | src/mainboard/intel/bayleybay_fsp/irqroute.h | 38 |
1 files changed, 23 insertions, 15 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/irqroute.h b/src/mainboard/intel/bayleybay_fsp/irqroute.h index 08552c534c..bce6f63bb6 100644 --- a/src/mainboard/intel/bayleybay_fsp/irqroute.h +++ b/src/mainboard/intel/bayleybay_fsp/irqroute.h @@ -40,22 +40,30 @@ *IR1Eh SIO INT(ABCD) - PIRQ BDEF *IR1Fh LPC INT(ABCD) - PIRQ HGBC */ + +/* PCIe bridge routing */ +#define BRIDGE1_DEV PCIE_DEV + +/* PCI bridge IRQs need to be updated in both tables and need to match */ +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV, E, F, G, H) + #define PCI_DEV_PIRQ_ROUTES \ - PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ - PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ - PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ - PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ - PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) /* * Route each PIRQ[A-H] to a PIC IRQ[0-15] |