soc/intel/xeon_sp/gnr: Add dimm_slot configuration

Add sample DIMM slot configuration table for avenuecity CRB
and beechnutcity CRB. This table will be used to fill SMBIOS
type 17 table.

TEST=Boot on intel/avenuecity CRB
It will help to update Locator, Bank Locator and Asset Tag
with the value described in dimm_slot_config_table

Change-Id: I53556c02eb75204994a1bcb42eccb940e83bd532
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 18 insertions, 0 deletions

diff --git a/src/mainboard/intel/avenuecity_crb/config/dimm_slot.c b/src/mainboard/intel/avenuecity_crb/config/dimm_slot.c
new file mode 100644
index 0000000000..00d5e13df4
--- /dev/null
+++ b/src/mainboard/intel/avenuecity_crb/config/dimm_slot.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <soc/dimm_slot.h>
+
+/*
+ * TODO: add the rest of DIMM slots
+ */
+static const struct dimm_slot_config dimm_slot_config_table[] = {
+	/* socket, channel, dimm, dev_locator, bank_locator, asset_tag */
+	{0, 0, 0, "CPU0_DIMM_A1", "BANK 0", "CPU0_DIMM_A1_AssetTag"},
+};
+
+const struct dimm_slot_config *get_dimm_slot_config_table(int *size)
+{
+	*size = ARRAY_SIZE(dimm_slot_config_table);
+	return dimm_slot_config_table;
+}