diff options
| author | Gang Chen <gang.c.chen@intel.com> | 2022-11-05 02:23:53 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-16 20:55:05 +0000 |
| commit | 921ddba69ee1513de162c2ea65018124de4c95f1 (patch) | |
| tree | 42360ca402e38ebc727bb22f62efda07d17d5956 /src/mainboard/intel/avenuecity_crb/config | |
| parent | 6258093575d63e3219bd32400e4801263ce92842 (diff) | |
mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/mainboard/intel/avenuecity_crb/config')
| -rw-r--r-- | src/mainboard/intel/avenuecity_crb/config/iio.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/intel/avenuecity_crb/config/iio.c b/src/mainboard/intel/avenuecity_crb/config/iio.c new file mode 100644 index 0000000000..117d604a2d --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/config/iio.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/iio.h> + +static const struct iio_pe_config iio_config_table[] = { + /* + * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated + * then port settings are listed accordingly. The minimal port elements are x2. + * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be + * disabled. + */ + {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { + /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ + _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5), + }}, +}; + +const struct iio_pe_config *get_iio_config_table(int *size) +{ + *size = ARRAY_SIZE(iio_config_table); + return iio_config_table; +} |