diff options
| author | Gang Chen <gang.c.chen@intel.com> | 2022-11-05 02:23:53 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-16 20:55:05 +0000 |
| commit | 921ddba69ee1513de162c2ea65018124de4c95f1 (patch) | |
| tree | 42360ca402e38ebc727bb22f62efda07d17d5956 /src/mainboard/intel/avenuecity_crb/bootblock.c | |
| parent | 6258093575d63e3219bd32400e4801263ce92842 (diff) | |
mb/intel/avenuecity_crb: Add GNR/SRF-AP 2S server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/mainboard/intel/avenuecity_crb/bootblock.c')
| -rw-r--r-- | src/mainboard/intel/avenuecity_crb/bootblock.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/intel/avenuecity_crb/bootblock.c b/src/mainboard/intel/avenuecity_crb/bootblock.c new file mode 100644 index 0000000000..e68d874c90 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/bootblock.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} |