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authorSubrata Banik <subratabanik@google.com>2024-02-20 20:15:20 +0530
committerSubrata Banik <subratabanik@google.com>2024-02-25 03:56:44 +0000
commit4bbace87aa6c239cbfea7703daaa0135467109cc (patch)
tree5b5af34c7381d46874004bdc0306747377b02533 /src/mainboard/intel/archercity_crb
parentf0277dbbe665e7af21868358b92bdfad617dcba2 (diff)
mb/google/rex/var/rex0: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing. Here are the two GPIOs to look for: * GPP_A19: Power Enable * GPP_A20: PERST The flow is presented as `stage (GPIO PAD/Value)` for easy understanding: bootblock (A20/0, A19/1) | v romstage (A20/1) Ideally, we don't need SSD power sequencing at ramstage, hence, remove the logic from ramstage. TEST=Able to build and boot google/rex0 using NVMe without any problems. S0ix and read/write from/to SSD are also normal. Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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