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authorDivya Sasidharan <divya.s.sasidharan@intel.com>2016-02-08 09:45:37 -0800
committerAaron Durbin <adurbin@chromium.org>2016-04-28 05:13:54 +0200
commitcbf1a0fec8b84dc936a35428b835501ad0f46a30 (patch)
treeba9fc31f4fe0b4b77885a9b35778f8324bb8b68e /src/mainboard/intel/amenia/dsdt.asl
parent4520c5e757cf280b7029a99adff60baed52493ce (diff)
mainboard/amenia: Enable Chrome EC Interface/Keyboard
Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/14468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/amenia/dsdt.asl')
-rw-r--r--src/mainboard/intel/amenia/dsdt.asl3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index ba4e7226fc..19e73605dd 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -36,4 +36,7 @@ DefinitionBlock(
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
+
+ #include "acpi/superio.asl"
+
}