mb/intel/adlrvp: Add ADL-P romstage mainboard code

List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD

TEST=Able to build and boot ADL-P RVP till ramstage early

Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
index 7a8f444fee..5288b6f832 100644
--- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
@@ -4,13 +4,25 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
+#include <soc/meminit.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+enum adl_boardid {
+	/* ADL-P LPDDR4 RVPs */
+	ADL_P_LP4_1 = 0x10,
+	ADL_P_LP4_2 = 0x11,
+	/* ADL-P DDR4 RVPs */
+	ADL_P_DDR4_1 = 0x14,
+	ADL_P_DDR4_2 = 0x3F,
+};
+
 /* The next set of functions return the gpio table and fill in the number of
  * entries for each table. */
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
 void variant_configure_early_gpio_pads(void);
 
+size_t variant_memory_sku(void);
+const struct mb_cfg *variant_memory_params(void);
 #endif /*__BASEBOARD_VARIANTS_H__ */