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| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-19 15:56:58 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-22 07:25:09 +0000 |
| commit | e9fa37894e59a35deeb897dcb323765d53603754 (patch) | |
| tree | 829a26c9e43a21071ad36c7bdd38f366b2899352 /src/mainboard/intel/adlrvp/romstage_fsp_params.c | |
| parent | 12e2e0e60933f0d4042087f13758ac5c1ae8d226 (diff) | |
soc/intel/xeon_sp: Define all SMI_STS bits
As per document 336067-007US (C620 PCH datasheet), add macros for all
bits in the SMI_STS register. These will be used in common code.
Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c')
0 files changed, 0 insertions, 0 deletions