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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-10-28 22:28:07 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-12-01 07:49:47 +0000 |
| commit | ae81d59ecaf050f7e14adb136560e993a98164cf (patch) | |
| tree | 7d81c6e58c85605d91520fa15d12fff8a9ba94e0 /src/mainboard/intel/adlrvp/romstage_fsp_params.c | |
| parent | 4cb8776c31ceb4a5b9e353b2e9b2a4f751e1dc54 (diff) | |
mb/intel/adlrvp: Add support for LPDDR5
This patch adds LPDDR5 memory configuration parameters to FSP.
TEST=Able to pass FSP-M MRC training on LPDDR5 RVP.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 672c59743e..2f03cb4e84 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -31,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) int board_id = get_board_id(); const bool half_populated = false; - const struct spd_info lpddr4_spd_info = { + const struct spd_info lp4_lp5_spd_info = { .read_type = READ_SPD_CBFS, .spd_spec.spd_index = get_spd_index(), }; @@ -56,7 +56,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) break; case ADL_P_LP4_1: case ADL_P_LP4_2: - memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated); + case ADL_P_LP5: + memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); break; default: die("Unknown board id = 0x%x\n", board_id); |