diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-28 13:50:19 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-11-05 07:29:44 +0000 |
| commit | 70296654825ddf5dfbe4980f385e8617c009a97e (patch) | |
| tree | b46db1e853bca66a0fb4a2b9f14b686c9dc0944e /src/mainboard/intel/adlrvp/romstage_fsp_params.c | |
| parent | 1410224cf476ed5e666deffcbbc455055632add1 (diff) | |
mb/intel/adlrvp: Add support for DDR5 memory
This patch adds DDR5 memory configuration parameters to FSP.
TEST=Able to build and boot ADLRVP with DDR5 memory.
Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 209ee6a222..672c59743e 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -36,7 +36,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) .spd_spec.spd_index = get_spd_index(), }; - const struct spd_info ddr4_spd_info = { + const struct spd_info ddr4_ddr5_spd_info = { .read_type = READ_SMBUS, .spd_spec = { .spd_smbus_address = { @@ -51,7 +51,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); + case ADL_P_DDR5: + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: |