diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2022-05-27 20:21:38 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-14 17:57:38 +0000 |
| commit | 91bc6d1da79b0c48d39770be84cdb2b2afde3050 (patch) | |
| tree | 5abb8ff0d5e9e0d680f77011a31c66af3392b21d /src/mainboard/intel/adlrvp/memory_rpl.c | |
| parent | 39c0e157315f631d6dae75fc99f9879ee469bcb0 (diff) | |
mb/intel/adlrvp: Add new upd setting for ADL RVP with Raptor Lake
Currently, ADL FSP headers and RPL FSP headers differ. Set a RPL only
upd for adlrvp with Raptor Lake silicon. This code can be removed once
ADL and RPL start using the same FSP.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e69323949233aa8c325a757b28b9d80cbdf4322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/memory_rpl.c')
| -rw-r--r-- | src/mainboard/intel/adlrvp/memory_rpl.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/memory_rpl.c b/src/mainboard/intel/adlrvp/memory_rpl.c new file mode 100644 index 0000000000..a541fbf1e2 --- /dev/null +++ b/src/mainboard/intel/adlrvp/memory_rpl.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> + +#include "board_id.h" + +void rpl_memory_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + + int board_id = get_board_id(); + + switch (board_id) { + case ADL_P_LP4_1: + case ADL_P_LP4_2: + case ADL_P_DDR4_1: + case ADL_P_DDR4_2: + case ADL_P_DDR5_1: + case ADL_P_DDR5_2: + return; + case ADL_P_LP5_1: + case ADL_P_LP5_2: + mem_cfg->Lp5BankMode = 1; + return; + default: + } +} |