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authorSubrata Banik <subrata.banik@intel.com>2021-02-20 13:52:52 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-02-22 07:26:14 +0000
commit40f53f4b8790c72247901d05e4369ca3e04b28f8 (patch)
treec2955430aec95fd28fd05cd73151fff0eb3c5678 /src/mainboard/intel/adlrvp/include
parentcbcae2744abcc38296106ff87897a5c02f267989 (diff)
mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/include')
-rw-r--r--src/mainboard/intel/adlrvp/include/baseboard/variants.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index 9cb8640860..295e1b1e3b 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -15,7 +15,8 @@ enum adl_boardid {
/* ADL-P DDR5 RVPs */
ADL_P_DDR5 = 0x12,
/* ADL-P LPDDR5 RVP */
- ADL_P_LP5 = 0x13,
+ ADL_P_LP5_1 = 0x13,
+ ADL_P_LP5_2 = 0x17,
/* ADL-P DDR4 RVPs */
ADL_P_DDR4_1 = 0x14,
ADL_P_DDR4_2 = 0x3F,