From 40f53f4b8790c72247901d05e4369ca3e04b28f8 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 20 Feb 2021 13:52:52 +0530 Subject: mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17 Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/include/baseboard/variants.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/adlrvp/include') diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9cb8640860..295e1b1e3b 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -15,7 +15,8 @@ enum adl_boardid { /* ADL-P DDR5 RVPs */ ADL_P_DDR5 = 0x12, /* ADL-P LPDDR5 RVP */ - ADL_P_LP5 = 0x13, + ADL_P_LP5_1 = 0x13, + ADL_P_LP5_2 = 0x17, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, -- cgit v1.2.3