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authorCliff Huang <cliff.huang@intel.corp-partner.google.com>2022-04-28 18:38:44 -0700
committerFelix Held <felix-coreboot@felixheld.de>2022-06-10 13:13:03 +0000
commit6c6be42c9fe1e03550aae6bf33bd8357021831b9 (patch)
tree997f07ab1802cb36d21664df4d94b8b5548239b7 /src/mainboard/intel/adlrvp/gpio.c
parentedbbabcbe7d3f3dd4e636ab7f363b22687c0399e (diff)
mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVP
Use clock src and clock req to 7 for x4 slot. Remove free running clock setting for clock 6. Configure gpio for source clock OEB native function going to x4 slot. BUG=b:233252409 BRANCH=firmware-brya-14505.B TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check the device. ex: 58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01) NOTE: The bus number varies. Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com> Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/gpio.c')
-rw-r--r--src/mainboard/intel/adlrvp/gpio.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 92a8c30420..e4483d2257 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -67,10 +67,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_B4, 1, PLTRST),
/* M.2_PCH_SSD_PWREN */
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
- /* SRCCLK_OEB7 */
- PAD_CFG_GPO(GPP_A7, 0, PLTRST),
- /* SRCCLK_OEB6 */
- PAD_CFG_GPO(GPP_E5, 0, PLTRST),
/* CAM1_RST */
PAD_CFG_GPO(GPP_R5, 1, PLTRST),
@@ -189,8 +185,6 @@ static const struct pad_config gpio_table[] = {
/* I2S0_RXD */
PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
- /* I2S2_SCLK */
- PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
/* I2S2_SFRM */
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* I2S2_TXD */