From 6c6be42c9fe1e03550aae6bf33bd8357021831b9 Mon Sep 17 00:00:00 2001 From: Cliff Huang Date: Thu, 28 Apr 2022 18:38:44 -0700 Subject: mb/intel/adlrvp: x4 slot support (SD card support) for Adl-P RVP Use clock src and clock req to 7 for x4 slot. Remove free running clock setting for clock 6. Configure gpio for source clock OEB native function going to x4 slot. BUG=b:233252409 BRANCH=firmware-brya-14505.B TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check the device. ex: 58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01) NOTE: The bus number varies. Signed-off-by: Cliff Huang Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik --- src/mainboard/intel/adlrvp/gpio.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/mainboard/intel/adlrvp/gpio.c') diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 92a8c30420..e4483d2257 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -67,10 +67,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B4, 1, PLTRST), /* M.2_PCH_SSD_PWREN */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), - /* SRCCLK_OEB7 */ - PAD_CFG_GPO(GPP_A7, 0, PLTRST), - /* SRCCLK_OEB6 */ - PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* CAM1_RST */ PAD_CFG_GPO(GPP_R5, 1, PLTRST), @@ -189,8 +185,6 @@ static const struct pad_config gpio_table[] = { /* I2S0_RXD */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - /* I2S2_SCLK */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* I2S2_SFRM */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* I2S2_TXD */ -- cgit v1.2.3