diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2021-02-10 18:07:46 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:24:56 +0000 |
| commit | b1a128fc88803fa902ab7e78f41b749b3bb13f05 (patch) | |
| tree | f35c7e9a7164b84125f32611066fedd12994ff53 /src/mainboard/intel/adlrvp/devicetree.cb | |
| parent | bc1941f17860a53ba24774a0d58e0d78f040cf30 (diff) | |
mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.
Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index eb7be69ca1..d0cb5f16ac 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -14,6 +14,9 @@ chip soc/intel/alderlake # FSP configuration + # Enable CNVi BT + register "CnviBtCore" = "true" + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 @@ -212,7 +215,6 @@ chip soc/intel/alderlake device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end - device pci 10.2 on end # CNVi: BT device pci 10.6 off end # THC0 device pci 10.7 off end # THC1 device pci 11.0 off end |