diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2024-02-19 11:45:26 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-22 13:39:53 +0000 |
| commit | 9c40215ef264e056e9db6dcf019affdd832bfc57 (patch) | |
| tree | b5906d08805522ba011a980fc37877886ccf4088 /src/mainboard/intel/adlrvp/Kconfig | |
| parent | fb401e74da0cd03ef2ee9dc8b2dc8863a5c25a84 (diff) | |
mb/intel/adlrvp: Remove ADLRVP_M mainboard
These boards are not commerically available so can be removed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/intel/adlrvp/Kconfig')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Kconfig | 30 |
1 files changed, 4 insertions, 26 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 41beefa55f..1083ce2b9c 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -64,23 +64,6 @@ config BOARD_INTEL_ADLRVP_P_MCHP select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_ALDERLAKE_PCH_P -config BOARD_INTEL_ADLRVP_M - select BOARD_INTEL_ADLRVP_COMMON - select DRIVERS_UART_8250IO - select MAINBOARD_USES_IFD_EC_REGION - select SOC_INTEL_ALDERLAKE_PCH_M - -config BOARD_INTEL_ADLRVP_M_EXT_EC - select BOARD_INTEL_ADLRVP_COMMON - select DRIVERS_INTEL_PMC - select FW_CONFIG - select FW_CONFIG_SOURCE_CHROMEEC_CBI - select INTEL_LPSS_UART_FOR_CONSOLE - select MAINBOARD_HAS_TPM2 - select SOC_INTEL_ALDERLAKE_PCH_M - select SPI_TPM - select TPM_GOOGLE_CR50 - config BOARD_INTEL_ADLRVP_N select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_UART_8250IO @@ -125,15 +108,12 @@ config VARIANT_DIR default "adlrvp_rpl" if BOARD_INTEL_ADLRVP_RPL default "adlrvp_rpl_ext_ec" if BOARD_INTEL_ADLRVP_RPL_EXT_EC default "adlrvp_p_mchp" if BOARD_INTEL_ADLRVP_P_MCHP - default "adlrvp_m" if BOARD_INTEL_ADLRVP_M - default "adlrvp_m_ext_ec" if BOARD_INTEL_ADLRVP_M_EXT_EC default "adlrvp_n" if BOARD_INTEL_ADLRVP_N default "adlrvp_n_ext_ec" if BOARD_INTEL_ADLRVP_N_EXT_EC config GBB_HWID string depends on CHROMEOS - default "ADLRVPM TEST 4471" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC default "ADLRVPN TEST 7673" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC default "ADLRVPP TEST 2418" @@ -149,7 +129,6 @@ config MAINBOARD_FAMILY default "Intel_adlrvp" config DEVICETREE - default "devicetree_m.cb" if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC default "devicetree_n.cb" if BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_N_EXT_EC default "devicetree.cb" @@ -161,8 +140,7 @@ config DIMM_SPD_SIZE choice prompt "ON BOARD EC" - default ADL_INTEL_EC if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_N || BOARD_INTEL_ADLRVP_RPL - default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC + default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC help This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC @@ -184,21 +162,21 @@ config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC - select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC || BOARD_INTEL_ADLRVP_N_EXT_EC + select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_N_EXT_EC config UART_FOR_CONSOLE int default 0 config DRIVER_TPM_SPI_BUS - default 0x2 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC + default 0x2 if BOARD_INTEL_ADLRVP_RPL_EXT_EC config USE_PM_ACPI_TIMER default n if BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_N config TPM_TIS_ACPI_INTERRUPT int - default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC || BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3) + default 67 if BOARD_INTEL_ADLRVP_RPL_EXT_EC # GPE0_DW2_3 (GPP_E3) config GEN3_EXTERNAL_CLOCK_BUFFER bool |