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authorPatrick Georgi <patrick.georgi@coresystems.de>2009-08-11 17:35:02 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2009-08-11 17:35:02 +0000
commitb339e10f04869a3d8da31e7d52831c32c57302a2 (patch)
tree9876043ec4255e1dcf619890eba579872273564f /src/mainboard/iei/pcisa-lx-800-r10
parent401c8d1da2a5292649498ec3a2c8414bd8ecd62c (diff)
Enable CBFS everywhere. All boards compiled for me (abuild tested),
and we will fix issues as they appear. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iei/pcisa-lx-800-r10')
-rw-r--r--src/mainboard/iei/pcisa-lx-800-r10/Options.lb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
index 9dac6822f4..051ffd56ea 100644
--- a/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
+++ b/src/mainboard/iei/pcisa-lx-800-r10/Options.lb
@@ -85,7 +85,7 @@ default CONFIG_IRQ_SLOT_COUNT = 9
default CONFIG_PIRQ_ROUTE = 1
default CONFIG_HAVE_OPTION_TABLE = 0
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = 128 * 1024
+default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
default CONFIG_USE_DCACHE_RAM = 1
default CONFIG_DCACHE_RAM_BASE = 0xc8000
default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
@@ -111,5 +111,5 @@ default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
# CBFS
#
#
-default CONFIG_CBFS=0
+default CONFIG_CBFS=1
end