Add support for the IEI NOVA-4899R 5.25 SBC mainboard (patch submitted by

Luis Correia <luis.f.correia@gmail.com>). The code is loosely based on
the Eaglelion 5bcm mainboard.

Warning: this is work in progress!

As of now, it does boot with serial console only (no vga), and two ethernet
cards work sometimes. This has to do with the IRQ assignments, which are a
complete mess. USB is now apparently working, but I can't make any device
to be recognized.

The PCI slot is still unusable due to the IRQ thing.

Audio, other serial ports, irda, floppy and paralell port support is
unknown aka untested yet.

(closes #32)

Signed-off-by: Luis Correia <luis.f.correia@gmail.com> 
Acked-by: Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 205 insertions, 0 deletions

diff --git a/src/mainboard/iei/nova4899r/Config.lb b/src/mainboard/iei/nova4899r/Config.lb
new file mode 100644
index 0000000000..ee4d31c21c
--- /dev/null
+++ b/src/mainboard/iei/nova4899r/Config.lb
@@ -0,0 +1,205 @@
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E 
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc 
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/amd/model_gx1/cpu_setup.inc
+mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit ./auto.inc
+
+##
+## Include the secondary Configuration files 
+##
+#dir /pc80
+#config chip.h
+
+chip northbridge/amd/gx1
+  device pci_domain 0 on 
+    device pci 0.0 on end
+      chip southbridge/amd/cs5530
+  			register "audio_irq" = "5"
+  			register "unwanted_vpci[0]" = "0x80007E00"	# USB/UDC
+	   		register "unwanted_vpci[1]" = "0x80007F00"	# USB/OTG
+	 	    register "unwanted_vpci[2]" = "0"	# End of list has a zero
+
+        device pci 12.0 on
+          chip superio/winbond/w83977tf
+            device pnp 2e.0 on		# Keyboard
+               io 0x60 = 0x60
+               io 0x62 = 0x64
+              irq 0x70 = 1
+            end
+            device pnp 2e.1 on		# Mouse
+              irq 0x70 = 12
+            end
+            device pnp 2e.2 on		# RTC
+               io 0x60 = 0x70
+              irq 0x70 = 8
+            end
+            device pnp 2e.3 off		# FDC
+            end
+            device pnp 2e.4 on		# Parallel Port
+               io 0x60 = 0x378
+              irq 0x70 = 7
+            end
+            device pnp 2e.5 on		# COM2
+               io 0x60 = 0x2f8
+              irq 0x70 = 3
+            end
+            device pnp 2e.6 on		# COM1
+               io 0x60 = 0x3f8
+              irq 0x70 = 4
+            end
+            device pnp 2e.7 on		# GPIO
+               io 0x60 = 0xe0
+            end
+            device pnp 2e.8 on		# Power Management
+               io 0x60 = 0xe800
+            end
+            register "com1" = "{115200}"
+            register "com2" = "{115200}"
+          end
+        device pci 12.1 on  end		# SMI
+        device pci 12.2 on  end		# IDE
+        device pci 12.3 on  end 	# Audio
+       
+      end
+
+      # VGA onboard
+      device pci 12.4 on 
+      chip drivers/pci/onboard
+          device pci 12.4 on end
+          register "rom_address" = "0xfffc0000" #256k image
+          #register "rom_address" = "0xfff80000" #512k image
+          #register "rom_address" = "0xfff00000" #1M image
+      end	# VGA 
+      end	# VGA 
+
+      device pci 0a.0 on  end 	# ETH0
+      device pci 0b.0 on  end 	# ETH1
+      device pci 0c.0 on  end 	# ETH2
+      device pci 0f.0 on  end 	# ETH3
+      
+      device pci 13.0 on  	# USB
+      end
+      
+    end
+  end
+
+  chip cpu/amd/model_gx1
+  end
+
+end
+