diff options
author | Marc Jones <marcj303@gmail.com> | 2010-09-13 19:24:38 +0000 |
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committer | Marc Jones <marc.jones@amd.com> | 2010-09-13 19:24:38 +0000 |
commit | 738347e7c3f9ba059cb56740703c9b513744aac6 (patch) | |
tree | d1f6bd6f22037287d6eb07fec5ffe5a03df30b7f /src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl | |
parent | 2b28614cc5021a0f3b20d3b8df6ac0d7813c1196 (diff) |
IEI Kino mainboard support based on Mahogany Fam10.
svn copy amd/mahogany iei/kino-780am2-fam10; then apply the patch.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl')
-rw-r--r-- | src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl b/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl new file mode 100644 index 0000000000..6a1b002474 --- /dev/null +++ b/src/mainboard/iei/kino-780am2-fam10/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } |