Add support for the IEI JUKI-511P and IEI ROCKY-512 half-size boards.

Both are very similar, thus both use the JUKI-511P target.

Linux with patches from Juergen Beisert
(http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html)
boots and work fine (ide, usb, ethernet, serial, keyboard and sound
work normally).

Problems:
 - Filo loads a bzImage only from ide0 (ide1 doesn't work yet).
 - Video doesn't work, yet.

Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 167 insertions, 0 deletions

diff --git a/src/mainboard/iei/juki-511p/Config.lb b/src/mainboard/iei/juki-511p/Config.lb
new file mode 100644
index 0000000000..53b1982fd1
--- /dev/null
+++ b/src/mainboard/iei/juki-511p/Config.lb
@@ -0,0 +1,167 @@
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+default ROM_SIZE = 256 * 1024 
+default ROM_SECTION_SIZE   = ROM_SIZE
+default ROM_SECTION_OFFSET = 0
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E 
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc 
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+mainboardinit cpu/x86/16bit/reset16.inc 
+ldscript /cpu/x86/16bit/reset16.lds 
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/amd/model_gx1/cpu_setup.inc
+mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit ./auto.inc
+
+##
+## Include the secondary Configuration files 
+##
+#dir /pc80
+#config chip.h
+
+chip northbridge/amd/gx1
+  device pci_domain 0 on
+    device pci 0.0 on end
+      chip southbridge/amd/cs5530
+
+        device pci 12.0 on
+          chip superio/winbond/w83977f
+            device pnp 3f0.0 on		# FDC
+              irq 0x70 = 6
+            end
+            device pnp 3f0.1 on		# Parallel port
+              io 0x60 = 0x378
+              irq 0x70 = 7
+            end
+            device pnp 3f0.2 on		# COM1
+              io 0x60 = 0x3f8
+              irq 0x70 = 4
+            end
+            register "com1" = "{115200}"
+            device pnp 3f0.3 on		# COM2
+              io 0x60 = 0x2f8
+              irq 0x70 = 3
+            end
+            register "com2" = "{115200}"
+            device pnp 3f0.4 on		# RTC
+              io 0x60 = 0x070
+              irq 0x70 = 8
+            end
+            device pnp 3f0.5 on		# Keyboard
+              io 0x60 = 0x60
+              io 0x62 = 0x64
+              irq 0x70 = 1		# Int  1 for PS/2 keyboard
+              irq 0x72 = 12		# Int 12 for PS/2 mouse
+            end
+            device pnp 3f0.6 off	# IR
+            end
+            device pnp 3f0.7 off	# GPIO1
+            end
+            device pnp 3f0.8 off	# GPIO
+            end
+          end
+        device pci 12.1 on end		# SMI
+        device pci 12.2 on end		# IDE
+        device pci 12.3 on end		# Audio
+        device pci 12.4 on end		# VGA onboard
+
+      end
+
+      device pci 0e.0 on end		# ETH0
+      device pci 13.0 on end		# USB
+
+    end
+  end
+
+  chip cpu/amd/model_gx1
+  end
+
+end
+