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authorBernhard M. Wiedemann <corebootbmw@lsmod.de>2010-05-30 12:56:17 +0000
committerStefan Reinauer <stepan@openbios.org>2010-05-30 12:56:17 +0000
commit6e554de0988fb1fd3e02aca6b6f2fc10c8fdc7ee (patch)
treeba9b96395e63bad1e1bfdd5ecd2d0cf9cc99ce42 /src/mainboard/ibase/mb899/rtl8168.c
parent1c60c88679f692dee5e547e58b4124c8639d4f07 (diff)
This patch adds support for mainboard iBASE:MB899
based on Kontron 986LCD-M changed superIO chip to w83627ehg, dropping MIDI dropped second superIO at 4e changed superIO-addr from 2e to 4e adjusted irq_tables.c and devicetree.cb dropped setup of 3xGBit-Ethernet adjusted IRQ-map (using values from mainboard/intel/d945gclf) disabled parts about HD-audio (missing on that board) Signed-off-by: Bernhard M. Wiedemann <corebootbmw@lsmod.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/ibase/mb899/rtl8168.c')
-rw-r--r--src/mainboard/ibase/mb899/rtl8168.c49
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mainboard/ibase/mb899/rtl8168.c b/src/mainboard/ibase/mb899/rtl8168.c
new file mode 100644
index 0000000000..101099ba02
--- /dev/null
+++ b/src/mainboard/ibase/mb899/rtl8168.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This code should work for all ICH* southbridges with a NIC. */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+static void nic_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "Initializing 88E8053 Gigabit Ethernet\n");
+ // Nothing to do yet, but this has to be here to keep
+ // coreboot from trying to execute an option ROM.
+}
+
+static struct device_operations nic_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = nic_init,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver rtl8169_nic __pci_driver = {
+ .ops = &nic_ops,
+ .vendor = 0x11ab,
+ .device = 0x4362,
+};
+
+