diff options
author | Riku Viitanen <riku.viitanen@protonmail.com> | 2023-12-13 23:36:20 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-21 16:12:40 +0000 |
commit | e1914693ceae31241353fa2c490f4485024367da (patch) | |
tree | c9777704dcdec85dcf427be0872f5224f1707ed0 /src/mainboard/hp/snb_ivb_desktops | |
parent | 69686564ec5d34efd63d5c06557cb3b2753b5673 (diff) |
mb/hp: Move compaq_elite_8300_usdt into snb_ivb_desktops variants
Tested to still boot, SeaBIOS -> Void Linux
Change-Id: Idc61e5d17f4c71fc50cf87c60a5063fc893c1d8c
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79544
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/hp/snb_ivb_desktops')
9 files changed, 321 insertions, 1 deletions
diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig b/src/mainboard/hp/snb_ivb_desktops/Kconfig index b79f748eef..d612c41d72 100644 --- a/src/mainboard/hp/snb_ivb_desktops/Kconfig +++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig @@ -17,6 +17,11 @@ config BOARD_HP_SNB_IVB_DESKTOPS_COMMON select SUPERIO_NUVOTON_NPCD378 select USE_NATIVE_RAMINIT +config BOARD_HP_COMPAQ_ELITE_8300_USDT + select BOARD_HP_SNB_IVB_DESKTOPS_COMMON + select SOUTHBRIDGE_INTEL_C216 + select BOARD_ROMSIZE_KB_16384 + config BOARD_HP_Z220_CMT_WORKSTATION select BOARD_HP_SNB_IVB_DESKTOPS_COMMON select BOARD_ROMSIZE_KB_16384 @@ -46,10 +51,12 @@ config MAINBOARD_DIR default "hp/snb_ivb_desktops" config VARIANT_DIR + default "compaq_elite_8300_usdt" if BOARD_HP_COMPAQ_ELITE_8300_USDT default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION config MAINBOARD_PART_NUMBER + default "HP Compaq Elite 8300 USDT" if BOARD_HP_COMPAQ_ELITE_8300_USDT default "HP Z220 CMT Workstation" if BOARD_HP_Z220_CMT_WORKSTATION default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION @@ -63,7 +70,7 @@ config DRAM_RESET_GATE_GPIO int default 60 -config USBDEBUG_HCD_INDEX +config USBDEBUG_HCD_INDEX # FIXME: check this on USDT int default 2 endif diff --git a/src/mainboard/hp/snb_ivb_desktops/Kconfig.name b/src/mainboard/hp/snb_ivb_desktops/Kconfig.name index 96fc8072dc..e448cd8c14 100644 --- a/src/mainboard/hp/snb_ivb_desktops/Kconfig.name +++ b/src/mainboard/hp/snb_ivb_desktops/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_HP_COMPAQ_ELITE_8300_USDT + bool "Compaq Elite 8300 USDT" + config BOARD_HP_Z220_CMT_WORKSTATION bool "Z220 CMT Workstation" diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/board_info.txt b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/board_info.txt new file mode 100644 index 0000000000..f47ea980b1 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/board_info.txt @@ -0,0 +1,6 @@ +Category: mini +ROM protocol: SPI +ROM socketed: n +ROM package: SOIC-16 +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/data.vbt b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/data.vbt Binary files differnew file mode 100644 index 0000000000..4e24edf093 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/data.vbt diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/early_init.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/early_init.c new file mode 100644 index 0000000000..d3b638ff73 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/early_init.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/nuvoton/npcd378/npcd378.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/gma-mainboard.ads b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/gma-mainboard.ads new file mode 100644 index 0000000000..74b50645e6 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/gpio.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/gpio.c new file mode 100644 index 0000000000..2ae852ae51 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/gpio.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/hda_verb.c b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/hda_verb.c new file mode 100644 index 0000000000..9c9415969f --- /dev/null +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ + 0x103c3398, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c3398), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), + AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), + AZALIA_PIN_CFG(0, 0x1d, 0x598301f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, 0x0221102f), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb new file mode 100644 index 0000000000..3511bbdeb2 --- /dev/null +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb @@ -0,0 +1,49 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + # Two SO-DIMMs + register "spd_addresses" = "{0, 0x52, 0, 0x50}" + + device domain 0 on + subsystemid 0x103c 0x3398 inherit + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x00fc0a01" + # 0x1: 2.5", 0x2: DVD, 0x4: mSATA + register "sata_port_map" = "0x7" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + }" + + device ref xhci on end + device ref lpc on + chip superio/common + device pnp 2e.ff on + chip superio/nuvoton/npcd378 + # Parallel port + device pnp 2e.1 off end + end + end + end + end + end + end +end |