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authorSubrata Banik <subratabanik@google.com>2024-07-09 23:15:39 +0530
committerSubrata Banik <subratabanik@google.com>2024-07-11 15:23:42 +0000
commit62347c4669937ea47200fd677ad0368f6e289495 (patch)
tree20f409d96cb9428f1dc1832409306660742cdc70 /src/mainboard/hp/folio_9480m/gma-mainboard.ads
parentea6b6acd01708ad88f4c6fefc4fd074790245f48 (diff)
soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-M
This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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