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authorIru Cai <mytbk920423@gmail.com>2020-09-08 19:50:55 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-11-10 06:16:05 +0000
commit85d0e7611a5cf9dcbf7d82deb54cc7e1e6fc79e8 (patch)
tree4725fb3f1538cbf09df121b42d08a24d586c9864 /src/mainboard/hp/folio_9480m/devicetree.cb
parent43cc3c0273a165da17c50dad68c009ea557c9462 (diff)
mb/hp: Add HP EliteBook Folio 9480m
The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. We also need to leave the end of the OEM flash content untouched, so the default ROM size is set to 12MiB instead of 16MiB, and we need to modify the IFD when flashing. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/hp/folio_9480m/devicetree.cb')
-rw-r--r--src/mainboard/hp/folio_9480m/devicetree.cb88
1 files changed, 88 insertions, 0 deletions
diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb
new file mode 100644
index 0000000000..bd81d38197
--- /dev/null
+++ b/src/mainboard/hp/folio_9480m/devicetree.cb
@@ -0,0 +1,88 @@
+chip northbridge/intel/haswell
+ register "dq_pins_interleaved" = "true"
+ register "ec_present" = "true"
+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_panel_power_backlight_off_delay" = "1"
+ register "gpu_panel_power_backlight_on_delay" = "1"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "500"
+ register "gpu_panel_power_up_delay" = "2000"
+ register "gpu_pch_backlight_pwm_hz" = "200"
+ register "usb_xhci_on_resume" = "true"
+ device cpu_cluster 0 on
+ chip cpu/intel/haswell
+ register "c1_battery" = "2"
+ register "c2_battery" = "3"
+ register "c3_battery" = "9"
+
+ register "c1_acpower" = "2"
+ register "c2_acpower" = "3"
+ register "c3_acpower" = "9"
+
+ device lapic 0 on end
+ device lapic 0xacac off end
+ end
+ end
+ device domain 0x0 on
+ subsystemid 0x103c 0x22da inherit
+ device pci 00.0 on end # Host bridge
+ device pci 02.0 on end # Internal graphics VGA controller
+ device pci 03.0 on end # Mini-HD audio
+
+ chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
+ register "gen1_dec" = "0x007c0201"
+ register "gen2_dec" = "0x000c0101"
+ register "gen4_dec" = "0x000402e9"
+ register "xhci_default" = "1"
+ register "sata_ahci" = "1"
+ register "sata_port1_gen3_dtle" = "0x6"
+ # SATA(1), M.2(3)
+ register "sata_port_map" = "0xa"
+ device pci 13.0 off end # Intel Smart Sound DSP
+ device pci 14.0 on end # xHCI Controller
+ device pci 15.0 off end # Serial I/O DMA
+ device pci 15.1 off end # I2C0
+ device pci 15.2 off end # I2C1
+ device pci 15.3 off end # GSPI0
+ device pci 15.4 off end # GSPI1
+ device pci 15.5 off end # UART0
+ device pci 15.6 off end # UART1
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 17.0 off end # SDIO
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on # PCIe Port #4, WLAN
+ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
+ "M.2 2230" "SlotDataBusWidth1X"
+ end
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1f.0 on # LPC bridge
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ # This laptop uses MEC1322, but it has the same interface
+ # as the KBC1126 laptops
+ chip ec/hp/kbc1126
+ register "ec_data_port" = "0x62"
+ register "ec_cmd_port" = "0x66"
+ register "ec_ctrl_reg" = "0x81"
+ register "ec_fan_ctrl_value" = "0x6b"
+ device pnp ff.1 off end
+ end
+ end
+ device pci 1f.2 on end # SATA Controller (AHCI)
+ device pci 1f.3 on end # SMBus
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end