mainboard/hp: Add HP Elitebook 2760p

The code is generated by autoport.

The flash chip is socketed beside the WLAN slot. The EHCI debug port
is on right side of the laptop beside the RJ11 connector.

Things that work:
- memory: 0+8G, 4G+8G
- Linux (Linux Mint 18.1 with Linux 4.4)
- native graphics init + SeaBIOS payload with SeaVGABIOS
- all 3 USB ports
- WLAN
- WWAN
- SD card reader
- expresscard
- S3 suspend and resume
- internal flashing after IFD is unlocked and coreboot is flashed
- keyboard, trackpoint and touchpad
- fan control
- AC and battery status

Issues:
- Wacom digitizer does not work (even after I add it in DSDT)
- GRUB payload will freeze (in all Elitebooks, including chainloading GRUB
  from SeaBIOS)

Things that are not tested:
- smart card reader
- cable modem

(EC) blobs:

This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the
flash chip. You can use the tools in util/kbc1126 to extract them
from OEM firmware, and use the following configuration to insert
them to coreboot image:

  -> Chipset
    -> Add firmware images for KBC1126 firmware

Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 76 insertions, 0 deletions

diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
new file mode 100644
index 0000000000..0d48f58e7f
--- /dev/null
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/hp/kbc1126/ec.h>
+
+void pch_enable_lpc(void)
+{
+	/*
+	 * CNF2 and CNF1 for Super I/O
+	 * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC
+	 */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN,
+			CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
+	/* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */
+	pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);
+}
+
+void rcba_config(void)
+{
+	RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 },
+	{ 1, 1, 0 },
+	{ 1, 1, 1 },
+	{ 1, 1, 1 },
+	{ 1, 0, 2 },
+	{ 1, 1, 2 },
+	{ 0, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 1, 4 },
+	{ 1, 0, 4 },
+	{ 0, 0, 5 },
+	{ 1, 1, 5 },
+	{ 0, 0, 6 },
+	{ 1, 1, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+	kbc1126_enter_conf();
+	kbc1126_mailbox_init();
+	kbc1126_kbc_init();
+	kbc1126_ec_init();
+	kbc1126_com1_init();
+	kbc1126_pm1_init();
+	kbc1126_exit_conf();
+	kbc1126_disable4e();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}